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CXD1199AQ
CD-ROM DECODER For the availability of this product, please contact the sales office.
Description The CXD1199AQ is a CD-ROM decoder LSI with a built-in ADPCM decoder. Features * Supports CD-ROM, CD-I and CD-ROM XA formats * Real-time error correction * Supports double speed playback * Connectable with standard SRAM of up to 1 M-bits (128 K-byte) * All audio output sampling frequencies : 132.3 kHz (built-in oversampling filter) * De-emphasis digital filter * Digital attenuator * Intel CPU 80 series host interface * Operates on 3.5 V Applications CD-ROM drives Structure Silicon gate CMOS IC 100 pin QFP (Plastic)
Absolute Maximum Ratings (Ta=25 C) * Supply voltage VDD -0.5 to +7.0 V * Input voltage VI -0.5 to VDD +0.5 V * Output voltage VO -0.5 to VDD +0.5 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage VDD +3.5 to +5.5 * Operating temperature Topr (+5.0 typ.) -20 to +75
V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E93Z06A78-TE
MDB0-7, P
Block Diagram
43-45, 48-52, 55-63 66 67-75 31 - DMA FIFO 39 23 XHCS 24 HA0 25 HA1 26 HINT PRIORITY RESOLVER HOST. I/F 27 XHRD 30 XHWR DESCRAMBLER CDP I/F SYNC CONTROL HOST DMA GALOIS FIELD SYNDROME GEN ECC CORRECTOR 41 HDRQ 42 XHAC ADPCM DECORDER 91 DATO 92 LRCO DAC I/F Sub CPU I/F DIGITAL FILTER CLOCK GEN 93 WCKO 94 BCKO 95 MUTE 22 XHRS ADDRESS GEN DMA SEQUENCER 1, 2, 5-10 D0-7 11 12 13 14 XCS XRD XINT XWR 16-20 A0-A4 88 EMP 21, 46, 47, 96-100 TD0-7 HD0-7, P
MA0-16 XMWR XMOE 64
3 VDD 28 53 78
4 15 29 40 GND 54 65 79 90
LRCK 84
DATA 85
--2--
BCLK 86
C2PO 87
XTL2 76
XTL1 77
CKSL 82
RMCK 83
CLK 80
HCLK 81
XRST 89 CXD1199AQ
CXD1199AQ
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Symbol D0 D1 VDD GND D2 D3 D4 D5 D6 D7 XCS XRD XWR XINT GND A0 A1 A2 A3 A4 TD0 XHRS XHCS HA0 HA1 HINT XHRD VDD GND XHWR HD0 HD1 HD2 HD3 HD4 I/O I/O I/O -- -- I/O I/O I/O I/O I/O I/O I I I O -- I I I I I I/O O I I I O I -- -- I I/O I/O I/O I/O I/O Description Sub CPU data bus Sub CPU data bus Power supply (+5 V) GND Sub CPU data bus Sub CPU data bus Sub CPU data bus Sub CPU data bus Sub CPU data bus Sub CPU data bus IC select negative logic signal from sub CPU Sub CPU strobe negative logic signal to read this IC internal register Sub CPU strobe negative logic signal to write this IC internal register Interrupt request negative logic signal from IC to sub CPU GND Sub CPU address Sub CPU address Sub CPU address Sub CPU address Sub CPU address Test I/O Negative logic signal indicating that IC has been reset from host; open drain output IC select negative logic signal from host Host address signal Host address signal Interrupt request negative logic signal to host; open drain output Host strobe negative logic signal to read this IC internal register Power supply (+5 V) GND Host strobe negative logic signal to read this IC internal register Host data bus Host data bus Host data bus Host data bus Host data bus
--3--
CXD1199AQ
Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
Symbol HD5 HD6 HD7 HDP GND HDRQ XHAC MA0 MA1 MA2 TD1 TD2 MA3 MA4 MA5 MA6 MA7 VDD GND MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15 MA16 XMOE GND XMWR MDB0 MDB1 MDB2 MDB3
I/O I/O I/O I/O I/O -- O I O O O I/O I/O O O O O O -- -- O O O O O O O O O O -- O I/O I/O I/O I/O
Description Host data bus Host data bus Host data bus Host data bus GND Host DMA request positive logic signal Host DMA acknowledge negative logic signal Buffer memory address (LSB) Buffer memory address Buffer memory address Test I/O Test I/O Buffer memory address Buffer memory address Buffer memory address Buffer memory address Buffer memory address Power supply (+5 V) GND Buffer memory address Buffer memory address Buffer memory address Buffer memory address Buffer memory address Buffer memory address Buffer memory address Buffer memory address Buffer memory address Buffer memory output enable negative logic signal GND Buffer memory write enable negative logic signal Buffer memory data bus Buffer memory data bus Buffer memory data bus Buffer memory data bus
--4--
CXD1199AQ
Pin No. 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Symbol MDB4 MDB5 MDB6 MDB7 MDBP XTL2 XTL1 VDD GND CLK HCLK CKSL RMCK LRCK DATA BCLK C2PO EMP XRST GND DATO LRCO WCKO BCKO MUTE TD7 TD6 TD5 TD4 TD3
I/O I/O I/O I/O I/O I/O O I -- -- O O I I I I I I I I -- O O O O O I/O I/O I/O I/O I/O
Description Buffer memory data bus Buffer memory data bus Buffer memory data bus Buffer memory data bus Buffer memory data bus (for error flag) Crystal oscillation circuit output Crystal oscillation circuit output (16.9344 MHz) Power supply (+5 V) GND 16.9344 MHz clock output 8.4672 MHz clock output Clock select signal for CD-ROM decoder Clock signal for CD-ROM decoder LR clock signal from CD DSP (for discriminating L, R channels) Data signal from CD DSP DATA pin strobe clock signal (bit clock) Error flag (C2 pointer) positive logic signal from CD DSP Emphasis ON positive logic signal from CD DSP Reset negative logic signal GND Data signal to DAC (D/A converter) LR clock signal to DAC Word clock signal to DAC Bit clock signal to DAC Mute positive logic signal Test I/O Test I/O Test I/O Test I/O Test I/O
--5--
CXD1199AQ
Electrical Characteristics DC characteristics Item TTL input level pin 1 High level input voltage TTL input level pin 1 Low level input voltage CMOS input level pin 2 High level input voltage CMOS input level pin 2 Low level input voltage CMOS Schmitt input level pin 3 High level input voltage CMOS Schmitt input level pin 3 Low level input voltage CMOS Schmitt input level pin 3 Input voltage hysteresis TTL Schmitt input level pin 4 High level input voltage TTL Schmitt input level pin 4 Low level input voltage TTL Schmitt input level pin 4 Input voltage hysteresis Bidirectional pin with pull-up resistance 5 Input current Input pin with pull-up resistance 6 Input current High level output voltage 7 Low level output voltage 7 Input leakage current 8 Output leakage current 9 Oscillation cell 10 High level input voltage Oscillation cell Low level input voltage Oscillation cell Logic threshold value Oscillation cell Feedback resistance value Oscillation cell High level output voltage Oscillation cell Low level output voltage Symbol VIH1 VIL1 VIH2 VIL2 VIH4 VIL4 VIH4-VIL4 VIH5 VIL5 VIH5-VIL4 IIL3 IIL4 VOH1 VOL1 I IOZ VIH4 VIL4 LVTH RFB VOH2 VOL2 VIN=0 V VIN=0 V -90 -40 0.4 -200 -100 -440 -240 2.2 V 0.8 V 0.6 0.8 VDD 0.2 VDD 0.7 VDD 0.3 VDD (VDD=5 V10 %, VSS=0 V, Topr=-20 to 75 C) Conditions Min. 2.2 0.8 Typ. Max. Unit V V V V V V V V V V A A V V A A V V V V V
IOH=-2 mA VDD-0.8 IOL=4 mA VIN=VSS or VDD -10 High-impedance -40 state 0.7 VDD 0.5 VDD 1M
0.4 10 40
0.3 VDD VIN=VSS or VDD IOH=-3 mA IOL=3 mA 250 K 0.5 VDD 2.5 M 0.5 VDD
--6--
CXD1199AQ
AC characteristics Item TTL input level pin 1 High level input voltage TTL input level pin 1 Low level input voltage CMOS input level pin 2 High level input voltage CMOS input level pin 2 Low level input voltage CMOS Schmitt input level pin 3 High level input voltage CMOS Schmitt input level pin 3 Low level input voltage CMOS Schmitt input level pin 3 Input voltage hysteresis TTL Schmitt input level pin 4 High level input voltage TTL Schmitt input level pin 4 Low level input voltage TTL Schmitt input level pin 4 Input voltage hysteresis Bidirectional pin with pull-up resistance 5 Input current Input pin with pull-up resistance 6 Input current High level output voltage 7 Low level output voltage 7 Input leakage current 8 Output leakage current 9 Oscillation cell 10 High level input voltage Oscillation cell Low level input voltage Oscillation cell Logic threshold value Oscillation cell Feedback resistance value Oscillation cell High level output voltage Oscillation cell Low level output voltage Symbol VIH1 VIL1 VIH2 VIL2 VIH4 VIL4 VIH4-VIL4 VIH5 VIL5 VIH5-VIL4 IIL3 IIL4 VOH1 VOL1 I IOZ VIH4 VIL4 LVTH RFB VOH2 VOL2 VIN=0 V VIN=0 V Conditions
(VDD=3.5 V, VSS=0 V, Topr=-20 to 75 C) Min. 2.2 0.6 0.7 VDD 0.3 VDD 0.8 VDD 0.2 VDD 0.5 2.2 V 0.6 V 0.3 -20 -10 -50 -25 -110 -60 Typ. Max. Unit V V V V V V V V V V A A V V A A V V V V V
IOH=-1.6 mA VDD-0.8 IOL=3.2 mA VIN=VSS or VDD -10 High-impedance -40 state 0.7 VDD 0.5 VDD 2.5 M
0.4 10 40
0.3 VDD VIN=VSS or VDD IOH=-1.3 mA IOL=1.3 mA 1.2 M 0.5 VDD 5M 0.5 VDD
--7--
CXD1199AQ
1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
D7 to 0, A4 to 0, XWR, XRD, XCS, MDB7 to 0, MDBP, HD7 to 0, HDP, TD7 to 0 DATA, LRCK, C2PO, EMP, CKSL, RMCK BCKL, XRST, CKSL A4 to 0, XWR, XRD, XCS, HA1, HA0, XHWR, XHRD, XHCS, XHAC D7 to 0, MDB7 to 0, MDBP, HD7 to 0, HDP, TD7 to 0 HA1, HA0, XHWR, XHRD, XHCS, XHAC All output pins except XTL2. All input pins except 5, 6 and XTL1. HINT input : XTL1; output : XTL2
I/O capacitance Item Input pin Output pin I/O pin Symbol CIN COUT COUT Min. Typ.
(VDD=VI=0 V, f=1 MHz) Max. 9 11 11 Unit pF pF pF
--8--
CXD1199AQ
AC Characteristics (VDD=5 V10 %, VSS=0 V, Topr=-20 to 75 C, output load=50 pF) Value in parentheses in the tables for VDD=3.5 V, VSS=0 V, Topr=-20 to +75 C and output load=50 pF. Others for VDD=5 V10 % and VDD=3.5 V. 1. Sub CPU interface (1) Read
A0 Thar XCS Trr1 XRD D7 to D0
Tsar
Tdrd
Tfrd
Item Address setup time (for XCS & XRD ) Address hold time (for XCS & XRD ) Data delay time (for XCS & XRD ) Data float time (for XCS & XRD ) Low level XRD pulse width (2) Write
A0
Symbol Tsar Thar Tdrd Tfrd Trr1
Min. 30 (70) 20 (50) 0 100 (150)
Typ.
Max.
60 (100) 15 (25)
Unit ns ns ns ns ns
XCS Tww1 XWR D7 to D0 Tsdw Thdw Thaw
Tsaw
Item Address setup time (for XCS & XWR ) Address hold time (for XCS & XWR ) Data setup time (for XCS & XWR ) Data hold time (for XCS & XWR ) Low level XWR pulse width
Symbol Tsaw Thaw Tsdw Thdw Tww1 --9--
Min. 30 (70) 20 (50) 40 (70) 10 (30) 50 (80)
Typ.
Max.
Unit ns ns ns ns ns
CXD1199AQ
2. CD DSP Interface (1) Read
BCKRED="H" Tbck BCLK Tbck
DATA Tsb1 LRCK C2PO Thb2 Tsb2 Thb1
BCKRED="L" Tbck Tbck
BCLK
DATA Tsb1 LRCK C2PO Thb2 Tsb2 Thb1
Item BCLK frequency BCLK pulse width Data setup time (for BCLK) Data hold time (for BCLK) LRCK, C2PO setup time (for BCLK) LRCK, C2PO hold time (for BCLK)
Symbol Fbck Tbck Tsb1 Thb1 Tsb2 Thb2
Min. 88 20 20 20 20
Typ.
Max. 11.3
Unit MHz ns ns ns ns ns
--10--
CXD1199AQ
3. Host interface (1) Read
HA0, 1 Thhar XHCS Thrd1 XHRD HD7 to 0, P
Thsar
Thdrd
Thfrd
Item Address setup time (for XHCS & XHRD ) Address hold time (for XHCS & XHRD ) Data delay time (for XHCS & XHRD ) Data float time (for XHCS & XHRD ) Low level XHRD pulse width
Symbol Thsar Thhar Thdrd Thfrd Thrd1
Min. 30 (70) 20 (50) 0 100 (150)
Typ.
Max.
60 (100) 15 (25)
Unit ns ns ns ns ns
(2) Write
HA0, 1 Thhar XHCS Thww1 XHWR HD7 to 0, P
Thsar
Thswd
Thhwd
Item Address setup time (for XHCS & XHWR ) Address hold time (for XHCS & XHWR ) Data setup time (for XHCS & XHWR ) Data hold time (for XHCS & XHWR ) Low level XHWR pulse width
Symbol Thsar Thhar Thswd Thhwd Thww1
Min. 30 (70) 20 (50) 40 (70) 10 (30) 60 (100)
Typ.
Max.
Unit ns ns ns ns ns
--11--
CXD1199AQ
4. Host DMA cycle (1) Read
HDRQ Tdar Tdad XHAC Thrd1 XHRD Tsac HD7 to 0, P Thac
Thdrd2
Thfrd2
Item HDRQ fall time (for XHAC ) HDRQ rise time (for XHAC ) XHAC setup time (for XHRD ) XHAC hold time (for XHRD ) Data delay time (for XHRD ) Data float time (for XHRD ) Low level XHRD pulse width (2) Write
HDRQ
Symbol Tdad Tdar Tsac Thac Thdrd2 Thfrd2 Thrd1
Min.
Typ.
Max. 45 (70) 45 (70)
5 (20) 0 (20) 0 100 (150) 60 (100) 15 (25)
Unit ns ns ns ns ns ns ns
Tdar Tdad XHAC Thww1 XHWR Tsac HD7 to 0, P Thac
Thswd2
Thhwd2
Item HDRQ fall time (for XHAC ) HDRQ rise time (for XHAC ) XHAC setup time (for XHWR ) XHAC hold time (for XHWR ) Data setup time (for XHWR ) Data hold time (for XHWR ) Low level XHWR pulse width
Symbol Tdad Tdar Tsac Thac Thswd2 Thhwd2 Thww1 --12--
Min.
Typ.
Max. 45 (70) 45 (70)
5 (20) 0 (20) 40 (70) 10 (30) 60 (100)
Unit ns ns ns ns ns ns ns
CXD1199AQ
5. DAC interface
Tbco BCKO
Tbco
DATO Tsbo WCKO LRCO Thbo Tsbo Thbo
Item BCKO frequency BCKO pulse width DATO, WCO1, WCO2, LRCO setup time (for BCKO ) DATO, WCO1, WCO2, LRCO hold time (for BCKO )
Symbol Fbco Tbco Tsbo Thbo
Min. 50 30 30
Typ. 8.4672
Max.
Unit MHz ns ns ns
--13--
CXD1199AQ
6. XTL1 and XTL2 pins (1) For self oscillation Item Oscillation frequency (2) When a pulse is input to XTL1
Tw
Symbol Fmax
Min.
Typ. 16.9344
Max.
Unit MHz
Twhx
Twlx Vihx Vidx 0.9
Vdd/2
Vihx 0.1 Vilx Tr Tf
Item High level pulse width Low level pulse width Pulse period Input high level Input low level Rise time Fall time
Symbol Twhx Twhx Tw Vihx Vihx Tr Tf
Min. 20 20 VDD-1.0
Typ.
Max.
59 0.8 15 15
Unit ns ns ns ns ns ns ns
Note) Synchronize the XTL1 clock signal with that of the CD DSP. (use the clock signal from the same oscillator)
7. RMCK pin Item Frequency Symbol Fmck Min. Typ. Max. 33.3 (23.4 with 3.5 V) Unit MHz
Note) The maximum RMCK frequency is 35.0 MHz when VDD is 5 V5 %. Playback at quadruple normal speed can be accommodated when a clock signal with a frequency double 16.9344 MHz or more is input to RMCK.
--14--
CXD1199AQ
Description of Functions 1. Pin Description The pin description by function is given below. 1-1. CD player interface (5 pins) This enables direct connection with the digital signal processor LSI for Sony's CD players. Digital signal processor LSI for CD applications is hereafter called "CD DSP". See 2-1-1 for the data formats. (1) DATA (DATA : input) Serial data stream from CD DSP. (2) BCLK (bit clock : input) Bit clock signal ; DATA signal strobe. (3) LRCK (LR clock : input) LR clock signal ; indicates left and right channels of DATA signals. (4) C2PO (C2 pointer : input) C2 pointer signal ; indicates that an error is contained in the DATA input. (5) EMP (emphasis : input) Emphasis positive logic signal ; indicates that emphasis has been applied to the data from CD DSP. 1-2. Buffer memory interface (28 pins) This is connected to a 32 K-byte (256 K-bit) or 128 K-byte (1 M-bit) standard SRAM. (1) XMWR (buffer memory write : output) Data write strobe negative logic output signal to buffer memory. (2) XMOE (buffer memory output enable : output) Data read strobe negative logic output signal to buffer memory. (3) MA0 to 16 (buffer memory address : output) Address signals to buffer memory. (4) MDB0 to 7, P (buffer memory data bus : bus) Data bus signals of buffer memory ; pulled up by standard 25 k resistance ; MDBP pin is left open when connected to an 8-bit/word SRAM. 1-3. Sub CPU interface (17 pins) (1) XWR (sub CPU write : input) Strobe negative logic input signal for writing IC internal register. (2) XRD (sub CPU read : input) Strobe negative logic input signal for reading IC internal register status. (3) D0 to 7 (sub CPU data bus : input/output) 8-bit data bus. (4) A0 to 4 (sub CPU address : input) Address signal for selecting IC internal register from sub CPU. (5) XINT (sub CPU interrupt : output) Interrupt request negative logic signal to sub CPU. (6) XCS (chip select : input) IC select negative logic signal from sub CPU.
--15--
CXD1199AQ
1-4. Host interface (17 pins) (1) HDRQ (host data request : output) DMA data request positive logic signal to host. (2) XHAC (host DMA acknowledge : input) DMA acknowledge negative logic signal from host. (3) XHWR (host write : input) Data write strobe input from host. (4) XHRD (host read : input) Data read strobe input from host. (5) XHCS (host chip select : input) Chip select negative logic signal from host. (6) HA0, 1 (host address : input) Address signals for selecting IC internal register from host. (7) HD0 to 7 (host data bus : input/output) Host data bus signals. (8) HDP (host data bus pointer : input/output) Host data bus positive logic signal for error pointer. (9) HINT (host interrupt : output) Interrupt request negative logic output signal to host ; open drain output. 1-5. DAC interface (4 pins) The output format to DAC is shown in Fig.1-1. (1) BCKO (bit clock output : output) Bit clock output signal to D/A converter. (2) WCKO (word clock output : output) Word clock output signal to D/A converter. (3) LRCO (LR clock output : output) LR clock output signal to D/A converter. (4) DATO (data output : output) Data output signal to D/A converter.
--16--
1234 MSB
1 23 4 5 6 7 8 9 10 11 12 13 14 15 16 1 23 45 6 7 89
17 L_CH LSB MSB R_CH
32
49
64
BCKO
10 11 12 13 14 15 16
DSTO
16
WCKO
LCKO
--17-- Fig. 1-1. D/A Converter Interface
CXD1199AQ
CXD1199AQ
1-6. Others (16 pins) (1) MUTE (mute : output) Outputs high when the DA data (DATO) is muted. (2) XRST (reset : input) Chip reset negative logic input signal. (3) XTL1 (crystal1 : input) (4) XTL2 (crystal2 : output) A 16.9344 MHz crystal oscillator is connected between XTL1 and XTL2. (The capacitor value depends on the crystal oscillator.) Alternatively, a 16.9344 MHz clock signal is input to the XTL1 pin. (5) CLK (clock : output) Outputs a 16.9344 MHz clock signal. The output can be fixed low when this signal is not used. (6) HCLK (half clock : output) Outputs an 8.4672 MHz clock signal. The output can be fixed low when this signal is not used. (7) CKSL (clock select : input) High or open : The IC is operated by the XTL1 clock. Low : The audio block (ADPCM decoder and digital filter) is operated by the XTL1 clock, and the CDROM decoder unit is operated by the RMCK clock. In this case, the slow mode described later is prohibited. This pin is pulled up by a 50 k standard resistor in the IC. (8) RMCK (ROM clock : input) When the CKSL pin is set low, the clock of the CD-ROM decoder unit is input. When it is high or open, fix the RMCK pin high or low. (9) XHRS (host reset : output) This pin is low when the IC has been reset by the host. It is an open drain output. (10) TD0 to 7 (test data 0 to 7 : input/output) The data pins for testing the IC. They are pulled up by a 25 k standard resistor and are normally left open. 1-7. Power supply pins (12 pins) VDD : 4 pins ; GND: 8 pins
--18--
CXD1199AQ
2. Sub CPU Registers 2-1. Write registers 2-1-1. DRVIF (drive interface) register This register controls the connection mode with the CD DSP. After the IC has been reset, the sub CPU sets this register according to the CD DSP to be connected. bit 7 : C2PL1ST (C2PO lower byte 1st) High : When two bytes of data are input, C2PO inputs the lower byte first followed by the upper byte. Low : When two bytes of data are input, C2PO inputs the upper byte first followed by the lower byte. Here, "upper byte" means the upper 8 bits including MSB from the CD DSP and "lower byte" means the lower 8 bits including LSB from the CD DSP. For instance, the header minute byte is the lower byte and the second byte, the upper byte. bit 6 : LCHLOW (Lch low) High : When LRCK is low, determined to be the left channel data. Low : When LRCK is high, determined to be the left channel data. bit 5 : BCKRED (rising edge of BCLK) High : The DATA is strobed at the rising edge of BCLK. Low : The DATA is strobed at the falling edge of BCLK. bits 4, 3 : BCKMD1, 0 (BCLK mode 1, 0) These bits are set according to the number of clocks output for BCLK during one WCLK cycle by the CD digital signal processor LSI (CD DSP).
BCKMD1 "L" "L" "H" BCKMD0 "L" "H" "X"
16 BCLKs/WCLK 24 BCLKs/WCLK 32 BCLKs/WCLK
bit 2 : High : Low : bits 1, 0
LSB1ST (LSB first) Connected with the CD DSP which outputs DATA with LSB first. Connected with the CD DSP which outputs DATA with MSB first. : Reserved Normally set below. Any change of each bit value in this register must be made in the decoder disable status. Table 2-1-1 shows the settings for bits 7 to 2 when this IC is connected to Sony's CD DSP. Figs. 2-1-1 (1) to (3) are input timing charts.
--19--
LRCK 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3
24
1
2
3
BCLK L15 L14 L13 L12 L11 L10 Lch MSB for Upper Byte for Lower Byte Lch LSB L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
DATA
R0
Rch LSB
C2PO
Fig. 2-1-1. (1) CDL30 and 35 Series Timing Chart
LRCK 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3
24
1
2
3
BCLK L15 L14 L13 L12 L11 L10 Lch MSB for Upper Byte for Lower Byte L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Lch LSB
--20--
5 6 7 8 9 Rch LSB for Upper Byte
DATA
R0
Rch LSB
C2PO
Fig. 2-1-1. (2) CDL40 Series Timing Chart (48-bit slot mode)
LRCK 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4
31 32
1
2
3
4
BCLK R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11R12 R13R14R15 Rch MSB for Lower Byte
L14 L15
DATA
Lch MSB
C2PO
CXD1199AQ
Fig. 2-1-1. (3) CDL40 Series Timing Chart (64-bit slot mode)
CXD1199AQ
Sony CD DSP CDL30 Series CDL35 Series CDL40 Series (48-bit slot mode) CDL40 Series (64-bit slot mode)
bit7 c2po L L L
bit6 lrck L L H
DR VIF register bit5 bit4 bit3 bedg bck1 bck0 L H L L L H H H X
bit2 lsb L L H
Timing chart
Fig. 2-1-1. (1) Fig. 2-1-1. (2) Fig. 2-1-1. (3)
Table 2-1-1. DR VIF Register Settings
--21--
CXD1199AQ
2-1-1. CONFIG1 (configuration 1) register This register is set depending on the IC peripheral hardware. The sub CPU sets this register after the IC has been reset. bit 7 : Reserved Normally set low. bit 6 : XSLOW The number of clock signals per DMA cycle is determined by this bit. High : 4 clock signals Low : 12 clock signals Set low when a low-speed SRAM is connected for VDD = 3.5 V. When XSLOW is low, erasure correction and double speed playback are prohibited. bit 5 : PRTYCTL (priority control) Set high when double speed playback with erasure correction executed is performed by setting the clock frequency of the CD-ROM decoder to 18 MHz or below. In this case, buffer access for ECC has priority and the rate of data transfer to the host is reduced. When a 9-bit/word SRAM has been connected to this IC, the C2 pointer is written from the BDBP pin into the buffer memory regardless of this bit value. bits 4, 3 : RAMSZ1, 0 (RAM size 1, 0) bit 2 : 9 BITRAM These bits are set depending on the size of the SRAM connected to the IC.
RAMSZ1 "L" "L" "L" "L" "H" "H" RAMSZ0 "L" "L" "H" "H" "L" "L" 9 BITRAM "L" "H" "L" "H" "L" "H" SRAM size 32 Kw x 8b 32 Kw x 9b 64 Kw x 8b 64 Kw x 9b 128 Kw x 8b 128 Kw x 9b
bit 1 : High : Low : bit 0 : High : Low :
CLKDIS (CLK disable) The CLK pin is fixed low. A 16.9344 MHz clock signal is output from the CLK pin. HCLKDIS (half CLK disable) The HCLK pin is fixed low. An 8.4672 MHz clock signal is output from the HCLK pin.
2-1-3. CONFIG2 (configuration 2) register This register is set depending on the IC peripheral hardware. The sub CPU sets this register after the IC has been reset. bits 7, 6 : Reserved Normally set low. bit 5 : SPECTL (sound parameter error control) bit 4 : SPMCTL (sound parameter majority control) These two bits control the processing of the sound parameters for ADPCM decoding playback. bit 3 : SMBF2 (sound map buffer 2) Indicates the number of buffer surfaces for the sound map ADPCM. High : 2 buffer surfaces for the sound map Low : 3 buffer surfaces for the sound map
--22--
CXD1199AQ
bit 2 : High : Low : bit 1 : High : Low : bit 0 :
DAMIXEN (digital audio mixer enable) Attenuator and mixer are not activated for CD-DA. Attenuator and mixer are activated for CD-DA. DACODIS (DAC out disable) Clock signals are output from the WCKO, LRCO and BCKO pins even for muting. The WCKO, LRCO and BCKO pins are set low for muting. Reserved Normally fixed low.
2-1-4. DECCTL (decoder control) register bit 7 : ENDLADR (enable drive last address) High : DLADR (drive last address) is enabled when this is high. When DADRC and DLADR become equal while the decoder is in the write-only, real-time correction or CD-DA mode, the data writing from the driver into the buffer is stopped. Low : DLADR (drive last address) is disabled when this is low. Even when DADRC and DLADR become equal while the decoder is in the write-only, real-time correction or CD-DA mode, data writing from the driver into the buffer is not stopped. bit 6 : ECCSTR (ECC strategy) High : Errors are corrected with consideration given to the error flags of the data. Low : Errors are corrected with no consideration given to the error flags of the data. In this case, there is no erasure correction. Set this bit low when the IC is connected to an 8-bit/word SRAM. bit 5 : MODESEL (mode select) bit 4 : FORMSEL (form select) When AUTODIST is low, the sector is corrected in the MODE or FORM indicated below.
MODESEL "L" "H" "H" FORMSEL "L" "L" "H"
MODE1 MODE2, FORM1 MODE2, FORM2
bit3 : AUTODIST (auto distinction) High : Errors are corrected according to the MODE byte and FORM bit read from the drive. Low : Errors are corrected according to the MODESEL and FORMSEL bits (bits 5 and 4). bits 2 to 0 : DECMD2 to 0 (decoder mode 2 to 0)
DECMD2 "L" "L" "H" "H" "H" "H" DECMD1 "L" "H" "L" "L" "H" "H" DECMD0 "X" "X" "L" "H" "L" "H"
Decoder disable Monitor-only mode Write-only mode Real-time correction mode Repeat correction mode CD-DA mode
When the CD-DA bit (bit 4) in the CHPCTL register is to be set high, set the decoder to the disable or CD-DA mode.
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CXD1199AQ
2-1-5. DLADR-L register 2-1-6. DLADR-M register 2-1-7. DLADR-H register While the decoder is in the write-only, real-time correction or CD-DA mode, the last address is set for the buffer write data from the drive. When the ENDLADR bit (bit 7) of the DECCTL register is high and the data from the drive is written into the address assigned by DLADR while the decoder is in any of the above modes, all subsequent writing in the buffer is prohibited. 2-1-8. CHPCTL (chip control) register bit 7 : SM MUTE (sound map mute) When this is set high, the audio output is muted for sound map ADPCM playback. bit 6 : RT MUTE (real-time mute) When this is set high, the audio output is muted for real-time ADPCM playback. bit 5 : CD-DA MUTE When bit 4 is high and this bit is also set high for CD-DA (digital audio) disc playback, the audio output is muted. When bit 4 is low, this bit has no effect on the audio output. bit 4 : CD-DA High : Set high for playing back the audio signals of a CD-DA (digital audio) disc. Setting this bit high is prohibited for ADPCM decoding playback. Low : Set low for not playing back the audio signals of a CD-DA (digital audio) disc. bit 3 : SWOPN (sync window open) High : A window for sync mark detection is opened. In this case, the sync protection circuit in the IC is disabled. Low : The window for sync mark detection is controlled by the sync protection circuit in the IC. bit 2 : RPSTART (repeat correction start) Sector error correction starts when the decoder is set to the repeat correction mode, making this bit high. This bit is automatically set low when correction starts. There is therefore no need for the sub CPU to reset low. bit 1 : DBLSPD (double speed) Set high for double speed playback. Before changing the bit value, switch the CD DSP mode (normal speed playback or double speed playback). bit 0 : RESERVED Normally set low. 2-1-9. INTMSK (interrupt mask) register By setting each bit of this register high, the interrupt request from the IC to the sub CPU is enabled depending on the corresponding interrupt status. (In other words, the INT pin is made active when its interrupt status is established.) The each bit value of this register has no effect on the corresponding interrupt status. bit 7 : DRVOVRN (drive overrun) The DRVOVRN status is established when the ENDLADR bit (bit 7) of the DECCTL register is set high and DADRC and DLADR become equal while the decoder is in the write-only or real-time correction mode. It is also established when they become equal while the decoder is in the CD-DA mode regardless of the ENDLADR bit value. bit 6 : DECTOUT (decoder time out) The DECTOUT status is established when the sync mark is not detected even after 3 sectors (40.6 ms at normal speed playback) have elapsed after the decoder has been set to the monitor-only, write-only or real-time correction mode. --24--
CXD1199AQ
bit 5
bit 4
bit 3 bit 2
bit 1 bit 0
: RSLTEMPT (result empty) The RSLTEMPT status is established when the host reads the result register and this register becomes empty. (This is used when the number of result bytes sent to the host is 9 or more.) : RTADPEND (real-time ADPCM end) The RTADPEND status is established when real-time ADPCM decoding is completed for one sector. : HDMACMP (host DMA complete) The HDMACMP status is established when DMA is completed by HXFRC. : DECINT (decoder interrupt) The DECINT status is established when the sync mark is detected or inserted while the decoder is in the write-only, monitor-only or real-time correction mode. However, it is not established if the sync mark interval is less than 2352 bytes while the window for its detection is open. The status is established each time one correction is completed when the decoder is in the repeat correction mode. : HSTCMND (host command) The HSTCMND status is established when the host writes a command in the command register. : HCRISD (host chip reset issued) The HCRISD status is established when the host clears the IC. When HCRISD is high, the XHRS pin is low.
2-1-10. CLRCTL (clear control) register When each bit of the register is set high, the corresponding chip, status, register, interrupt status and ADPCM playback are cleared. After clearing, the bit concerned is automatically set low. There is therefore no need for the sub CPU to reset low. bit 7 : CHPRST (chip reset) The inside of the IC is initialized when this bit is set high. It is automatically set low upon completion of the initialization. bit 6 : CLRBUSY (clear busy) The BUSYSTS bit of the HIFSTS register is cleared when this bit is set high. bit 5 : CLRRSLT (clear result) The RESULT register is cleared when this bit is set high. bit 4 : RTADPCLR (real-time ADPCM clear) (1) When this is set high for real-time ADPCM playback (when the RTADPBSY bit of the DECSTS register is high): * ADPCM decoding during playback is suspended. (Noise may be generated.) * The RTADPEND interrupt status is established. (Note) The RTADPEN bit (bit 7 of the ADPMNT register) must be set low before this bit is set high. (2) Setting this bit high when real-time ADPCM playback is not being performed has no effect whatsoever. bits 3 to 1 : Reserved Normally set low. bit 0 : RESYNC The CD DSP and this IC are synchronized when this bit is set high. Set the bit high by the sub CPU in the following cases: (1) After the DRVIF register has been set (2) After the DBLSPD bit (bit 1 of the CHPCTL register) has been set low. This bit is automatically set low when the CD DSP and this IC are synchronized.
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CXD1199AQ
2-1-11. CLRINT (clear interrupt status) register When each bit of this register is set high, the corresponding interrupt status is cleared. The bit concerned is automatically set low after its interrupt status has been cleared. There is therefore no need for the sub CPU to reset low. bit 7 : DRVOVRN (drive overrun) bit 6 : DECTOUT (decoder time out) bit 5 : RSLTEMP (reset empty) bit 4 : RTADPEND (real-time ADPCM end) bit 3 : HDMACMP (host DMA complete) bit 2 : DECINT (decoder interrupt) bit 1 : HSTCMND (host command) bit 0 : HCRISD (host chip reset issued) 2-1-12. HXFR-L (host transfer-low) register 2-1-13. HXFR-H (host transfer-high) register bit 7 : DISHXFRC (disable host transfer counter) High : The completion of the data transfer by HXFRC is disabled for data transfer between the host and buffer memory. Low : The completion of the data transfer by HXFRC is enabled for data transfer between the host and buffer memory. bits 6, 5 : Reserved bit 4 : HADR16 HADR bit 16 (MSB) bit 3 : HXFR11 HXFR (host transfer counter) bit 11 (MSB) bit 2 : HXFR10 HXFR bit 10 bit 1 : HXFR9 HXFR bit 9 bit 0 : HXFR8 HXFR bit 8 The HXFR (host transfer) register sets the number of data transferred between the host and buffer memory. The sub CPU sets this number when data is transferred between the host and buffer memory by setting the DISHXFRC bit low. 2-1-14. HADR-L register 2-1-15. HADR-M register 2-1-16. HADR-H register The HADR (host address) register is for the head addresses of data transfer between the host and buffer memory. 2-1-17. DADRC-L register 2-1-18. DADRC-M register
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CXD1199AQ
2-1-19. DADRC-H register This counter keeps the address for writing the data from the drive into the buffer. When drive data is written into the buffer, the DADRC value is output from MA0 to 16. DADRC is incremented each time 1 byte of data is written from the drive into the buffer. The sub CPU sets the head address for buffer writing into DADRC before the decoder operates in the writeonly, real-time correction or CD-DA mode. The sub CPU can set DADRC at any time. The contents of DADRC should not be changed while the decoder is operating in any of the above modes. 2-1-20. HIFCTL (host interface control) register bits 7 to 3 : Reserved The sub CPU sets these bits low. bit 2 : HINT#2 The value of this bit becomes that of HINTSTS#2 in the HINTSTS register on the host side. bit 1 : HINT#1 The value of this bit becomes that of HINTSTS#1 in the HINTSTS register on the host side. bit 0 : HINT#0 The value of this bit becomes that of HINTSTS#0 in the HINTSTS register on the host side. 2-1-21. RESULT register This register is used to transfer the command execution result to the host. It has an 8-byte FIFO configuration. 2-1-22. ADPMNT register bit 7 : RTADPEN (real-time ADPCM enable) The sub CPU sets this high to perform real-time ADPCM playback. bits 6 to 0 : The upper 7 bits (bits 16 to 10) of the sector head address are written into these bits to perform real-time ADPCM playback.
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CXD1199AQ
2-1-23. RTCI (real-time coding information) register Writes the coding information bytes when real-time ADPCM playback is performed. bit 6 : EMPHASIS Set high when an ADPCM sector where emphasis has been applied is played back. bit 4 : BITLNGTH (bit length) Indicates the bit length of the coding information for ADPCM playback. High : 8 bits Low : 4 bits bit 2 : FS (sampling frequency) Indicates the sampling frequency of ADPCM playback. High : 18.9 kHz Low : 37.8 kHz bit 0 : S/M (stereo/mono) Indicates the coding information stereo or mono for ADPCM playback. High : Stereo Low : Mono bits 7, 5, 3, 1 : Reserved Normally set low. All the write registers except INTMSK are 00HEX when the IC is reset (either hard or soft reset). All the bits in the INTMSK register except the HCRISD bit (bit 0) are low when the IC is reset. The HCRISD bit is set low by hard or by soft reset by the sub CPU. The HCRISD bit value is not affected by soft resetting by the host. "Hard reset" means that the XRST pin is set low; "soft reset" means that the IC is reset by the sub CPU or host.
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CXD1199AQ
2-2. Read registers In the descriptions of the ECCSTS, DECSTS, HDRFLG, HDR, SHDR and CMADR registers, the current sector denotes the sector with which these registers are valid for the decoder interrupt (DECINT). In the monitor-only or write-only mode, the sector sent from the CD DSP immediately before the decoder interrupt is called the current sector. In the real-time correction mode and repeat correction mode, the current sector is that in which error detection correction has been completed. 2-2-1. ECCSTS (ECC status) register bit 7 : EDCALL0 (EDC ALL 0) This is high when there are no error flags in all the 4 EDC parity bytes of the current sector and their values are all 00HEX. : ERINBLK (erasure in block) (1) When the decoder is operating in the monitor-only, write-only or real-time mode which prohibits erasure correction, this indicates that at least a 1-byte error flag (C2PO) has been raised in the data excluding the sync mark from the current sector CD DSP. (2) When the decoder is operating in the real-time correction mode which performs erasure correction, this indicates that at least a 1-byte error flag (MDBP) has been raised in the data excluding the sync mark from the current sector CD DSP. : CORINH (correction inhibit) This is high if the current sector MODE and FORM could not be determined when the AUTODIST bit of the DECCTL register is set high. ECC or EDC is not executed in this sector. The CORINH bit is invalid when AUTODIST is set low. It is high in any of the conditions below when the AUTODIST bit is set high. (1) When the C2 pointer of the MODE byte is high (2) When the MODE byte is a value other than 01HEX or 02HEX (3) When the MODE byte is 02HEX and the C2 pointer is high in the submode byte : CORDONE (correction done) Indicates that there is an error corrected byte in the current sector. : EDCOK Indicates that an EDC check has found no errors in the current sector. : ECCOK Indicates that there are no more errors from the header byte to P parity byte in the current sector. (Bit 2 = don't care in the MODE2, FORM2 sectors)
EDCOK "L" ECCOK "L" Description Error(s) present in current sector (1), (2) or (3) applies: (1) EDC overlocked (2) Error corrected (3) Error(s) present in header byte with FORM2 (1) EDC overlocked or (3) Error(s) present in P parity byte No error(s) in current sector
bit 6
bit 5
bit 4 bit 3 bit 2
"L"
"H"
"H" "H"
"L" "H"
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CXD1199AQ
bit 1 bit 0
: CMODE (correction mode) : CFORM (correction form) Indicates the MODE and FORM of the current sector the decoder has discriminated and corrected errors when the decoder is operating in the real-time correction or repeat correction mode.
CFORM "X" "L" "H" CMODE "L" "H" "H"
MODE1 MODE2, FORM1 MODE2, FORM2
2-2-2. DECSTS (decoder status) register bit 5 bit 1 : RTADPBSY (real-time ADPCM busy) This is high for real-time ADPCM playback. : SHRTSCT (short sector) Indicates that the sync mark interval was less than 2351 bytes. This sector does not remain in the buffer memory. : NOSYNC Indicates that the sync mark was inserted because one was not detected at the prescribed position.
bit 0
2-2-3. HDRFLG (header flag) register This register indicates the error flags of the header and sub header register bytes. 2-2-4. HDR (header) register This is a 4-byte register which indicates the current sector header byte. By setting the address to 03HEX and reading out the data in sequence, the sub CPU can ascertain the values of the current sector header bytes from the minute byte. 2-2-5. SHDR (sub header) register This is a 4-byte register which indicates the current sector sub header byte. By setting the address to 04HEX and reading out the data 4 times, the sub CPU can ascertain the values of the current sector sub header bytes in the sequence of the file, submode and data type bytes. The contents of the HDRFLG, HDR, SHDR registers indicate: (1) The corrected value in the real-time correction or repeat correction mode (2) Value of the raw data from the drive in the monitor-only or write-only mode The CMOME and CMODE bits (bits 1, 0) of ECCSTS indicate the FORM and MODE of the sector the decoder has discriminated by the raw data from the drive. Due to erroneous correction, the values of these bits may be at variance with those of the HDR register MODE byte and SHDR register submode byte bit 5. 2-2-6. CMADR (current minute address) register This register indicates the upper 7 bits of the buffer memory address where the minute byte of the current sector (after error correction) is written in bits 6 to 0. (Remaining address bits are all low.)
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CXD1199AQ
2-2-7. INTSTS (interrupt status) register The value of each bit in this register indicates that of the corresponding interrupt status. These bits are not affected by the values of the INTMSK register bits. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 : : : : : : : : DRVOVRN (drive overrun) DECTOUT (decoder time out) RSLTEMPT (RESULT empty) RTADPEND (real-time ADPCM end) HDMACMP (host DMA complete) DECINT (decoder interrupt) HSTCMND (host command) HCRISD (host chip reset issued)
2-2-8. ADPCI (ADPCM coding information) register bit 7 : MUTE This is high when the DA data is muted. bit 6 : EMPHASIS This is high when emphasis is applied to the ADPCM data. bit 5 : ADPBUSY This is high for ADPCM decoding. bit 4 : BITLNGTH (bit length) Indicates the bit length of the coding information for ADPCM playback. High : 8 bits Low : 4 bits bit 2 : FS (sampling frequency) Indicates the sampling frequency of ADPCM playback. High : 18.9 kHz Low : 37.8 kHz bit 0 : S/M (stereo/mono) Indicates the coding information stereo or mono for ADPCM playback. High : Stereo Low : Mono
2-2-9. HXFRC-L (host transfer counter-low) register 2-2-10. HXFRC-H (host transfer counter-high) register The HXFRC counter indicates the number of remaining bytes in the data to be transferred between the host and buffer memory. If sound map data is to be transferred before the data is transferred (immediately after the host has set the BFRD and BFWR bits (bits 7 and 6) of the HCHPCTL register high), 2304 (900HEX) is loaded into HXFRC. At any other time, the HXFR (sub CPU register) value is loaded. HXFRC is decremented when data is read from the buffer memory (BFRD is high) or when the IC accepts data from the host (BFWR is high). 2-2-11. HADRC-L (host address counter-low) register
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CXD1199AQ
2-2-12. HADRC-M (host address counter-middle) register This counter keeps the addresses which write or read the data with host into/from the buffer. If sound map data is to be transferred before the data is transferred (immediately after the host has set the BFRD and BFWR bits (bits 7 and 6) of the HCHPCTL register high), 600CHEX, 6A0CHEX or 740CHEX (1MRAM is low) is loaded into HADRC. At any other time, the HADR (sub CPU register) value is loaded. When data from the host is written into the buffer or data to the host is read from the buffer, the HADRC value is output from MA0 to 16. HADRC is incremented each time one byte of data from the drive is read from the buffer (BFRD is high) or written into the buffer (BFWR is high). The MSB (bit 16) of HADRC is read out from bit 4 of the HXFRC-H register. 2-2-13. DADRC-L (drive address counter-low) register 2-2-14. DADRC-M (drive address counter-middle) register The MSB (bit 16) of DADRC is read out from bit 5 of the HXFRC-H register. 2-2-15. HIFSTS (host interface status) register bit 7 : BUSYSTS (busy status) This has the same value as BUSYSTS (bit 7) of the host HSTS register. It is set high when the host writes a command into the command register and low when the sub CPU sets CLRBUSY of the CLRCTL register. : RSLWRDY (result write ready) The result register is not full when this bit is high. The sub CPU can write the result of the command execution into this register. : RSLEMPT (result empty) The result register is empty when this bit is high. It indicates that all the status sent from the sub CPU to the host (result register) have been read out by the host. : PRMRRDY (parameter read ready) The HSTPRM register is not empty when this bit is high. The sub CPU can read out the command parameters from the HSTPRM register. : DMABUSY (DMA busy) This is high when data is being transferred between the buffer memory and the host. It is high when the host sets BFRD (bit 7) or BFWR (bit 6) of the HCHPCTL register high. It is low in the case below: * When the data transfer FIFO (WRDATA, RDDATA registers) is empty after the level of HXFRC has dropped to 00HEX. : HINTSTS#2 (host interrupt status #2) This is high when the sub CPU writes data into HINT#2 (HIFCTL register bit 2) and low when the host writes "high" into CLRINT#2 (HCLRCTL register bit 2). It is used to monitor interrupts for the host. : HINTSTS#1 (host interrupt status #1) This is high when the sub CPU writes data into HINT#1 (HIFCTL register bit 1) and low when the host writes "high" into CLRINT#1 (HCLRCTL register bit 1). It is used to monitor interrupts for the host. : HINTSTS#0 (host interrupt status #0) This is high when the sub CPU writes data into HINT#0 (HIFCTL register bit 0) and low when the host writes "high" into CLRINT#0 (HCLRCTL register bit 0). It is used to monitor interrupts for the host.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
--32--
CXD1199AQ
2-2-16. HSTPRM (host parameter) register The command parameters from the host are read out from this register. The register has an 8-byte FIFO configuration. 2-2-17. HSTCMD (host command) register The command from the host are read out from this register.
REG DRVIF CONFIG 1 CONFIG 2 DECCTL DLADR-L DLADR-M DLADR-H CHPCTL INTMSK CLRCTL CLRINT HXFR-L HXFR-H HADR-L HADR-M DADRC-L DADRC-M DADRC-H ADR 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B bit7 C2PO L 1st "L" "L" EN DLADR bit7 bit15 "L" SM MUTE "L" DRV OVRN CHP RST DRV OVRN bit7 DIS HXFRC bit7 bit15 bit7 bit15 "L" "L" "L" "L" "L" bit7 "L" RTADP EN "L" "L" bit6 LCH LOW XSLOW "L" ECC STR bit6 bit14 "L" RT MUTE "L" DEC TOUT CLR BUSY DEC TOUT bit6 "L" bit6 bit14 bit6 bit14 "L" "L" "L" "L" "L" bit6 "L" bit16 "L" EMPHASIS bit5 BCK RED PRTY CTL SPE CTL MODE SEL bit5 bit13 "L" CDDA MUTE "L" RSLT EMPT CLR RSLT RSLT EMPT bit5 "L" bit5 bit13 bit5 bit13 "L" "L" "L" "L" "L" bit5 "L" bit15 "L" "L" bit4 BCK MD1 RAM SZ1 SPM CTL FORM SEL bit4 bit12 "L" CD-DA "L" RTADP END RTADP CLR RTADP END bit4 HADR bit16 bit4 bit12 bit4 bit12 "L" "L" "L" "L" "L" bit4 "L" bit14 "L" BIT LNGTH bit3 BCK MD0 RAM SZ0 SM BF2 AUTO DIST bit3 bit11 "L" SW OPEN "L" HDMA CMP "L" HDMA CMP bit3 bit11 bit3 bit11 bit3 bit11 "L" "L" "L" "L" "L" bit3 "L" bit13 "L" "L" bit2 LSB 1st 9 bit RAM DAMIX EN DEC MD2 bit2 bit10 "L" RPS TART "L" DEC INT "L" DEC INT bit2 bit10 bit2 bit10 bit2 bit10 "L" "L" "L" "L" HINT #2 bit2 "L" bit12 "L" FS bit1 "L" CLK DIS DACO DIS DEC MD1 bit1 bit9 "L" DBL SPD "L" HST CMND "L" HST CMND bit1 bit9 bit1 bit9 bit1 bit9 "L" "L" "L" "L" HINT #1 bit1 "L" bit11 "L" "L" bit0 "L" HCLK DIS "L" DEC MD0 bit0 bit8 bit16 "L" "L" HCR ISD RE SYNC HCR ISD bit0 bit8 bit0 bit8 bit0 bit8 bit16 "L" "L" "L" HINT #0 bit0 "L" bit10 "L" S/M
HIFCTL RESULT ADPMNT RTCI
Sub CPU write registers
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CXD1199AQ
bit6 bit7 ADR bit5 00 EDC ALL0 ERIN BLK COR INH -- -- 01 RTADP BSY SEC MIN 02 BLOCK bit6 bit7 03 bit5 bit6 bit7 04 bit5 bit16 -- 05 bit15 07 DRV OVRN DEC TOUT RSLT EMPT EMPHASIS -- 08 -- -- -- 09 -- bit6 bit7 0A HXFRC-L bit5 -- -- 0B HXFRC-H DADRC bit16 bit6 bit7 0C HADRC-L bit5 bit14 bit15 HADRC-M 0D bit13 bit6 bit7 0E DADRC-L bit5 bit14 bit15 DADRC-M 0F bit13 -- -- 10 -- 11 BUSY STS RSLT WRDY RSL EMPT HIFSTS bit7 12 HSTPRM bit5 bit6 bit7 13 HSTCMD bit5 bit6 REG ECCSTS DECSTS HDRFLG HDR SHDR CMADR INTSTS ADPCI
bit0 bit1 bit2 bit4 bit3 C FORM C MODE ECC OK COR DONE EDC OK SHRT SCT NO SYNC -- -- -- CI CHANNEL SUB MODE FILE MODE bit0 bit1 bit2 bit3 bit4 bit0 bit1 bit2 bit3 bit4 bit10 bit11 bit12 bit13 bit14 RTADP END HDMA CMP DEC INT HST CMND HCR ISD S/M -- FS BIT LNGTH -- -- -- -- -- -- bit0 bit1 bit2 bit4 bit3 bit8 bit9 bit10 bit11 HADRC bit16 bit0 bit1 bit2 bit3 bit4 bit8 bit9 bit10 bit11 bit12 bit0 bit1 bit2 bit3 bit4 bit8 bit9 bit10 bit11 bit12 -- -- -- -- -- PRM RRDY DMA BUSY HINT STS2 HINT STS1 HINT STS0 bit0 bit1 bit2 bit3 bit4 bit0 bit1 bit2 bit3 bit4
Sub CPU read registers
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CXD1199AQ
3. Host Registers 3-1. Write registers 3-1-1. ADDRESS register bits 7 to 2 : Reserved Normally set low. bits 1, 0 : RA1, 0 These are the address expansion bits. The host read/write register is selected according to the combination of these bits with the HA1 and 0 inputs. Refer to the table at the end of this section for the register selection methods. 3-1-2. COMMAND register This is the register in which the host writes the commands. When the host writes a command in it, an interrupt request can be output to the sub CPU. The control program specifies bit allocation and functions. 3-1-3. PARAMETER register The host writes the command parameters required to execute commands in this register. The register has an 8-byte FIFO configuration. 3-1-4. HCHPCTL (host chip control) register bit 7 : BFRD (buffer read) The transfer of (drive) data from the buffer memory to the host is started by setting this bit high. The bit is automatically set low upon completion of the transfer. : BFWR (buffer write) The transfer of data from the host to the buffer memory is started by setting this bit high. The bit is automatically set low upon completion of the transfer. : SMEN (sound map En) This is set high to perform sound map ADPCM playback.
bit 6
bit 5
3-1-5. WRDATA (write data) register This is the register for writing the data to the buffer memory from the host. Data can be written in the I/O mode or using DMAC. The register has a 2-byte FIFO configuration. 3-1-6. HINTMSK (HOST interrupt mask) register Setting each bit in this register high enables an interrupt request from the IC to the host depending on the corresponding interrupt status. The value of each bit has no effect on the corresponding interrupt status. bit 7 : Reserved bit 4 : ENBFWRDY (enable buffer write ready interrupt) bit 3 : ENBFEMPT (enable buffer write empty interrupt) bits 2 to 0 : ENINT#2 to 0 (enable interrupt #2 to 0)
--35--
CXD1199AQ
3-1-7. HCLRCTL (HOST clear control) register When each bit of this register is set high, the chip, status, register, interrupt status and interrupt request to the host generated by the status are cleared. bit 7 : CHPRST (chip reset) The inside of the IC is initialized by setting this bit high. The bit is automatically set low upon completion of the initialization of the IC. There is therefore no need for the host to reset low. When the inside of the IC is initialized by setting bit high, the XHRS pin is set low. bit 6 : CLRPRM (clear parameter) The parameter register is cleared by setting this bit high. The bit is automatically set low upon completion of the clearing for the parameter register. There is therefore no need for the host to reset low. bit 5 : SMADPCLR (sound map ADPCM clear) This bit is set high to terminate sound map ADPCM decoding forcibly. (1) When this bit has been set high for sound map ADPCM playback (when both SMEN and ADPBSY (HSTS register bit 2) are high): * ADPCM decoding during playback is suspended. (Noise may be generated). * The sound map and buffer management circuits in the IC are cleared, making the buffer empty. The BFEMPT interrupt status is established. (Note) Set the SMEN bit low at the same time as this bit is set high. (2) Setting this bit high when the sound map ADPCM playback is not being performed has no effect whatsoever bit 4 : CLRBFWRDY (clear buffer write ready interrupt) bit 3 : CLRBFEMPT (clear buffer write empty interrupt) bits 2 to 0 : CLRINT#2 to 0 (clear interrupt #2 to 0) bit 4 clears the corresponding interrupt status. 3-1-8. CI (coding information) register This sets the coding information for sound map playback. The bit allocation is the same as that for the coding information bytes of the sub header. bits 7, 5, 3, 1: Reserved bit 6 : EMPHASIS High : Emphasis ON Low : Emphasis OFF bit 4 : BITLNGTH High : 8 bits Low : 4 bits bit 2 : FS High : 18.9 kHz Low : 37.8 kHz bit 0 : S/M (stereo/mono) High : Stereo Low : Mono 3-1-9. ATV (attenuation value) register 0 3-1-10. ATV (attenuation value) register 1
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CXD1199AQ
3-1-11. ATV (attenuation value) register 2 3-1-12. ATV (attenuation value) register 3 The attenuation values are set in these registers.
ATV0 L ATV3 DF ATV1 ATV2 R
ADPCM DECODER
Setting 81HEX or higher into these registers is prohibited. When bits 7 to 0 of these registers are "b7" to "b0", the attenuation (dB) of the attenuator is as follows: Attenuation=20 log (b7 x 20 + b6 x 2-1 + b5 x 2-2 + b4 x 2-3 + b3 x 2-4 + b2 x 2-5 + b1 x 2-6 + b0 x 2-7) The relationship expressed in the above formula and ATV register settings is given in the following table.
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CXD1199AQ
Setting 80 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58 57 56
Attenuation 0.00 0.07 0.14 0.21 0.28 0.35 0.42 0.49 0.56 0.63 0.71 0.78 0.86 0.93 1.01 1.08 1.16 1.24 1.32 1.40 1.48 1.56 1.64 1.72 1.80 1.89 1.97 2.06 2.14 2.23 2.32 2.41 2.50 2.59 2.68 2.77 2.87 2.96 3.06 3.16 3.25 3.35 3.45
Setting 55 54 53 52 51 50 4F 4E 4D 4C 4B 4A 49 48 47 46 45 44 43 42 41 40 3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30 2F 2E 2D 2C 2B
Attenuation 3.56 3.66 3.76 3.87 3.97 4.08 4.19 4.30 4.41 4.53 4.64 4.76 4.88 5.00 5.12 5.24 5.37 5.49 5.62 5.75 5.89 6.02 6.16 6.30 6.44 6.58 6.73 6.88 7.03 7.18 7.34 7.50 7.66 7.82 7.99 8.16 8.34 8.52 8.70 8.89 9.08 9.28 9.47
Setting 2A 29 28 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00
Attenuation 9.68 9.89 10.10 10.32 10.55 10.78 11.02 11.26 11.51 11.77 12.04 12.32 12.60 12.90 13.20 13.52 13.84 14.19 14.54 14.91 15.30 15.70 16.12 16.57 17.04 17.54 18.06 18.62 19.22 19.87 20.56 21.32 22.14 23.06 24.08 25.24 26.58 28.16 30.10 32.60 36.12 42.14
Relationship between ATV register settings and attenuation (dB)
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CXD1199AQ
3-1-13. ADPCTL (ADPCM control) register bit 5 : CHNGATV (change ATV register) The host sets this bit high after the changes of the ATV 3 to 0 registers have been completed. The attenuator value in the IC is switched for the first time. There is no need for the host to set this bit low. The bit used to set the ATV3 to 0 registers of the host and to synchronize the IC audio playback. bit 0 ADPMUTE (ADPCM mute) Set high to mute the ADPCM sound for ADPCM decoding. bits 7, 6, 4 to 1 : Reserved Apart from ATV 2 and 0, all the write registers are initialized to 00HEX when reset (either hard or soft reset). The ATV 2 and 0 registers are initialized to 80HEX when reset.
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CXD1199AQ
3-2. Read registers 3-2-1. HSTS (host status) register bit 7 : BUSYSTS (busy status) This is high when the host writes a command into the command register and low when the sub CPU sets the CLRBUSY bit (bit 6) of the CLRCTL register. bit 6 : DRQSTS (data request status) Indicates to the host that the buffer memory data transfer request status is established. When transferring data in the I/O mode, the host should confirm that this bit is high before accessing the WRDATA or RDDATA register. bit 5 : RSLRRDY (result read ready) The result register is not empty when this bit is high. At this time, the host can read the result register. bit 4 : PRMWRDY (parameter write ready) The PARAMETER register is not full when this bit is high. At this time, the host writes data into the PARAMETER register. bit 3 : PRMEMPT (parameter empty) The PARAMETER register is empty when this bit is high. bit 2 : ADPBUSY (ADPCM busy) This bit is set high for ADPCM decoding. bits 1, 0 : RA1, 0 The values of the RA1 and 0 bits for the ADDRESS register can be read from these bits. 3-2-2. RESULT register The host reads the results of the command execution through this register. The register has ah 8-byte FIFO configuration. 3-2-3. RDDATA (read data) register This register is where the data from the buffer memory is written from the host. Data can be read in the I/O mode or using DMAC. The register has a 2-byte FIFO configuration. 3-2-4. HINTMSK (host interrupt mask) register The values written in the HINTMSK register can be read from this register.
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CXD1199AQ
3-2-5. HINTSTS (host interrupt status) register bit 4 : BFWRDY (buffer write ready) The BFWRDY status is established if there is area where writing is possible in the buffer of 1 sector or more for sound map playback. It is established in any of the following cases: (1) When the host has set the SMEN bit (bit 5) of the HCHPCTL register high (2) When there is sound map data area of 1 sector or more in the buffer memory (when the buffer is not full) after the sound map data equivalent to 1 sector from the host has been written into the buffer memory (3) When an area for writing the sound map data has been created in the buffer memory by the completion of the sound map ADPCM decoding of one sector bit 3 : BFEMPT (buffer empty) The BFEMPT status is established when there is no more sector data in the buffer memory upon completion of the sound map ADPCM decoding of one sector for sound map playback. bits 2 to 0 : INTSTS#2 to 0 The values of these bits are those of the corresponding bits for the sub CPU HIFCTL register.
bit5 bit6 bit0 bit7 bit1 bit4 bit3 bit2 "L" "L" RA0 "L" RA1 "L" "L" "L" bit5 bit6 bit0 bit7 bit1 bit4 bit3 bit2 bit5 bit6 bit0 bit7 bit1 bit4 bit3 bit2 SMEN BFWR "L" BFRD "L" "L" "L" "L" bit5 bit6 bit0 bit7 bit1 bit4 bit3 bit2 "L" "L" "L" ENBF WRDY ENBF EMPT EN INT#2 EN INT#1 EN INT#0 CHP RST CLR PRM SMADP CLR CLRBF WRDY CLRBF EMPT CLR INT#2 CLR INT#1 CLR INT#0 EMPHASIS S/M "L" "L" FS "L" BIT LNGTH "L" bit6 bit0 bit7 bit1 bit2 bit5 bit4 bit3 bit6 bit0 bit7 bit1 bit2 bit5 bit4 bit3 bit6 bit0 bit7 bit1 bit2 bit5 bit4 bit3 bit6 bit0 bit7 bit1 bit2 bit5 bit4 bit3 "L" ADP MUTE "L" "L" "L" CHNG ATV "L" "L"
ADR REG 0/ ADDRESS COMMAND 10 PARAMETER 20 HCHP CTL 30 11 WR DATA HINT MSK 21 HCLR CTL 31 12 CI 22 ATV0 32 ATV1 13 ATV2 23 ATV3 33 ADP CTL
Host write registers
bit4 bit5 bit6 bit7 bit0 ADR bit1 REG bit3 bit2 RA0 0/ BUSY STS DRQ STS RSL RRDY PRM WRDY PRM EMPT ADP BUSY RA1 HSTS bit5 bit6 bit7 bit0 1/ bit1 RESULT bit3 bit2 bit4 bit5 bit6 bit7 bit0 2/ bit1 RD DATA bit3 bit2 bit4 -- -- -- HINT MSK 3/0 ENBF WRDY ENBF EMPT EN ENT#2 EN ENT#1 EN ENT#0 -- -- -- HINT STS 3/1 BF WRDY BF EMPT INT STS#2 INT STS#1 INT STS#0
Host read registers Note) The left figures in the ADR column denote the HA1 and 0 pins and the right denote the RA1 and 0 pins.
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CXD1199AQ
Package Outline
Unit : mm
100PIN QFP (PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1 80 51 + 0.1 0.15 - 0.05
81
50
+ 0.4 14.0 - 0.1 17.9 0.4
15.8 0.4
A 100 31
1
0.65
+ 0.15 0.3 - 0.1
30 0.24 M + 0.35 2.75 - 0.15
+ 0.2 0.1 - 0.05
0.15
DETAIL A
0.8 0.2
0 to 15
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.7g
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